Tunneling emitter

ABSTRACT

An emitter has an electron supply layer and a tunneling layer formed on the electron supply layer. Optionally, an insulator layer is formed on the electron supply layer and has openings defined within in which the tunneling layer is formed. A cathode layer is formed on the tunneling layer to provide a surface for energy emissions of electrons and/or photons. Preferably, the emitter is subjected to an annealing process thereby increasing the supply of electrons tunneled from the electron supply layer to the cathode layer.

FIELD OF THE INVENTION

[0001] The invention is directed to field emission devices. Inparticular the invention is directed to the flat field emission emittersutilizing direct tunneling and their use in electronic devices.

BACKGROUND OF THE INVENTION

[0002] Several different field emission devices have been proposed andimplemented to create electron emissions useful for displays or otherelectronic devices such as storage devices. Traditionally, vacuumdevices with thermionic emission such as electron tubes required theheating of cathode surfaces to create the electron emission. Theelectrons are drawn in a vacuum space to an anode structure that is at apredetermined voltage potential to attract the electrons. For a displaydevice such as a cathode ray tube, the anode structure is coated withphosphors such that when an electron impinges on the phosphor, photonsare generated to create a visible image. Cold cathode devices such asspindt tips (pointed tips) have been used to replace the hot cathodetechnology. However, it has been difficult to reduce the size andintegrate several spindt tips while maintaining reliability. As the sizeis reduced, the spindt tip becomes more susceptible to damage fromcontaminants in the vacuum that are ionized when an electron strikes it.The ionized contaminant is then attracted to the spindt tip and collideswith it, thereby causing damage. To increase the life of the spindt tip,the vacuum space must have an increasingly high vacuum. A flat emitterhaving a larger emission surface can be operated reliably at lowervacuum requirements. However, for some applications, the amount ofcurrent density from conventional flat emitters is not high enough to beuseful. Thus a need exists to create a flat emitter that has highcurrent density that is also able to operate reliably in low vacuumenvironments.

SUMMARY

[0003] An emitter has an electron supply layer and a tunneling layerformed on the electron supply layer. Optionally, an insulator layer isformed on the electron supply layer and has openings defined within inwhich the tunneling layer is formed. A cathode layer is formed on thetunneling layer to provide a surface for energy emissions of electronsand/or photons. Preferably, the emitter is subjected to an annealingprocess thereby increasing the supply of electrons tunneled from theelectron supply layer to the cathode layer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004]FIG. 1 is an exemplary illustration of a tunneling emitterincorporating the invention.

[0005]FIG. 2 is an exemplary illustration of the use of the tunnelingemitter of FIG. 1 to create a focused electron beam.

[0006]FIG. 3 is an exemplary illustration of an integrated circuit thatincludes several tunneling emitters and an optical lens to create adisplay device.

[0007]FIG. 4 is an exemplary block diagram of an integrated circuit thatincorporates multiple tunneling emitters and control circuitry.

[0008]FIG. 5 is an exemplary illustration of a tunneling emitter on anintegrated circuit that includes a lens for focusing the energyemissions from the tunneling emitter.

[0009]FIG. 6 is an exemplary display that is created from an integratedcircuit that includes multiple tunneling emitters and an anode structurethat creates or passes photons.

[0010]FIG. 7 is an exemplary storage device that incorporates anintegrated circuit that includes multiple tunneling emitters for readingand recording information onto a rewriteable media.

[0011]FIG. 8 is a top view of an exemplary tunneling emitter.

[0012]FIG. 9 is an exemplary cross-sectional view of the tunnelingemitter shown in FIG. 8.

[0013]FIG. 10 is an exemplary block diagram of a computer thatincorporates at least one of the electronic devices, a display orstorage device, which incorporate the tunneling emitters of theinvention.

[0014]FIGS. 11A-11L are illustrations of exemplary steps used in anexemplary process to create the tunneling emitter of the invention.

[0015]FIGS. 12A and 12B are charts of exemplary annealing processes usedto optionally improve the tunneling emitters of the invention.

DETAILED DESCRIPTION OF THE PREFERRED AND ALTERNATE EMBODIMENTS

[0016] The present invention is directed to field emission emitters thatprovide high levels of emission current per square centimeter by using atunneling layer that has a sufficient thinness of less than about 500Angstroms to create a high electric field between an electron source anda flat cathode surface. Conventional flat emitter type devices have lowemission current per square centimeter of surface area and thus are notusable in several applications. The invention uses a thin deposition ofa metal cluster dielectric, preferably between 50 and 250 Angstroms,preferably about 100 Angstroms to create a barrier in which electronscan tunnel between the electron source and the cathode surface. By usingsuch a material, the emission current can be greater than 10 mAmps, 100mAmps, or 1 Amp per square centimeter which is one, two, or three ordersof magnitude, respectively, greater than that of conventional flatemitter technology. The actual emission rate will depend upon the designchoices of the type and thickness of material used for the tunnelinglayer. In addition to electron emissions, the invention is also able tocreate photon emissions that provides for additional uses for theemitter incorporating the invention. Further advantages and features ofthe invention will become more apparent in the following description ofthe invention, its method of making and various applications of use.

[0017] In the illustrations of this description, various parts of theemitter elements have not been drawn to scale. Certain dimensions havebeen exaggerated in relation to other dimensions in order to provide aclearer illustration and understanding of the present invention. For thepurposes of illustration, the embodiments illustrated herein are shownin two-dimensional views with various regions having depth and width. Itshould be understood that these region are illustrations only of aportion of a single cell of a device, which may include a plurality ofsuch cells arranged in a three-dimensional structure. Accordingly, theseregions will have three dimensions, including length, width, and depthwhen fabricated on an actual device.

[0018] Further, one aspect of the invention is that it can be fabricatedusing conventional integrated circuit thin-film technologies. Severaldifferent technologies exist to perform several of the process steps andcan be interchanged by those having skill in the art. For example,unless specifically called out, deposition of material can be by one ofseveral processes such as evaporation, sputtering, chemical vapordeposition, molecular beam epitaxy, photochemical vapor deposition, lowtemperature photochemical vapor deposition, and plasma deposition, toname a few. Additionally, several different etch technologies exist suchas wet etching, dry etching, ion beam etching, reactive ion etching, andplasma etching such as barrel plasma etching and planar plasma etchingto name some of the possible etching technologies. Choice of actualtechnologies used will depend on material used and cost criteria amongother factors.

[0019]FIG. 1 is an exemplary diagram of an emitter device 50, preferablya flat emitter for electron and photon emission, which includes anelectron source 10. On the electron source 10 is a tunneling layer 20.Preferably, the tunneling layer 20 is formed from a metal clusterdielectric such as tungsten silicon nitrate (WSiN) or tantalum oxide(TaO_(x)), titanium oxide (TiO_(x), where x=0.5 to 2.5). Also, tantalumaluminum oxynitride (TaAlO_(x)N_(y)), tantalum aluminum oxide(TaAlO_(x)), aluminum oxynitride (AlO_(x)N_(y)) or other transitionarymetal (TM) oxides or oxynitrides ((TM)O_(x) or (TM)O_(x)N_(y)) areenvisioned as being capable of use as tunneling layer 20. The tunnelinglayer preferably has a thickness less than 500 Angstroms and preferablythe thickness is within the range of about 50 to about 250 Angstroms,such as 100 Angstroms or less. The chosen thickness determines theelectrical field strength that the tunneling layer must be able towithstand and the desired emitter emission current. Disposed on thetunneling layer 20 is a cathode layer 14, preferably a thin-filmconductor such as platinum, gold, molybdenum, iridium, ruthenium,tantalum, chromium, or other refractive metals or alloys thereof.Preferably, the thickness of the cathode layer is 30 to 150 Angstroms.When a voltage source 24 having an emitter voltage V_(e) (about 3-10V)is applied to the cathode layer 14 and electron supply 10 via a contact12, electrons tunnel from the substrate 10 (an electron supply) to thecathode layer 14. Because of the thinness of the tunneling layer 20, theelectric field in which the electrons tunnel through is very strong andthe electron emission 16 from the surface of the cathode layer 14 isgreater than conventional designs. Also, photon emission 18 occurs alongwith the electron emission 16 to form the energy emission 22 from theemitter 50.

[0020] The electron field is calculated for various thicknesses as$\overset{\rightarrow}{E} = \frac{V_{e}}{t_{thickness}}$

[0021] where t_(thickness) is the thickness of tunneling layer 20. Forexample, for a V_(e)=10V, the electric field is equal to 10⁷ volts/meterfor a 100 Angstrom thickness in the tunneling layer,

[0022] Preferably, the tunneling layer 20 is sputter deposited. By usingmetal cluster dielectrics as the tunneling layer, a very high electricfield strength can be applied between the electron source 10 and thecathode layer 14 to achieve higher emission, because the metal clusterdielectrics withstand much higher electrical field strength withoutelectrical breakdown.

[0023]FIG. 2 is an exemplary diagram of a use for the emitter 50 ofFIG. 1. In this application, the electron emission 16 is focused by anelectrostatic focusing device or lens 28, exemplified as an aperture ina conductor that is set at predetermined voltage that can be adjusted tochange the focusing effect of the lens 28. Those skilled in the art willappreciate that lens 28 can be made from more than one conductor layerto create a desired focusing effect. The electron emission 16 is focusedby lens 28 into a focused beam 32 onto an anode structure 30. The anodestructure 30 is set at an anode voltage V_(a) 26 which magnitude variesfor an application depending on the intended use and the distance fromthe anode structure 30 to the emitter 50. For instance, with anodestructure 30 being a recordable medium for a storage device, V_(a) mightbe chosen to be between 500 and 1000 Volts. The lens 28 focuses theelectron emission 16 by forming an electric field 34 within itsaperture. By being set at a proper voltage from V_(e), the electronsemitted from the emitter 50 are directed to the center of the apertureand then further attracted to the anode structure 30 to form the focusedbeam 32.

[0024]FIG. 3 is an exemplary embodiment of a display 40 having anintegrated circuit 52 that includes multiple integrated emitters 100formed in an array of pixel groups. The integrated emitters 100 emitphoton emission 18, a visible light source, which is focused with anoptical lens 38 to a focused beam 32 that is viewable as an image. Theoptical lens 38 is preferably coated with a transparent conductingsurface, such as indium tin oxide, to capture electrons emitted from theemitters, thus forming a cathode layer on the lens.

[0025]FIG. 4 is an exemplary embodiment of an integrated circuit 52 thatincludes at least one integrated emitter 100 but preferably a pluralityof integrated emitters 100 arraigned in an array. An emitter controlcircuit 72 is integrated onto the integrated circuit 52 and used tooperate the at least one integrated emitter 100.

[0026]FIG. 5 is an exemplary embodiment of an integrated circuit 52 thatincludes an integrated emitter 100 and a lens array 48. The integratedcircuit 52 is formed on a conductive substrate 10, preferably heavilydoped silicon or a conductive material such as a thin film conductivelayer to provide an electron source. On the substrate 10 is disposed atunneling layer 20 having a thickness of less than 500 Angstroms,preferably about 100 Angstroms though 50 to 250 Angstroms is furtherpreferable for some applications. Different layers of semiconductorthin-film materials are applied to the substrate 10 and etched to formthe integrated emitter 100. Disposed on the tunneling layer 20 is acathode layer 14, preferably a thin-film conductive layer of platinum,gold, molybdenum, iridium, ruthenium, tantalum, chromium, or otherrefractive metals or alloys thereof, but preferably substantiallyplatinum. The cathode layer 14 forms a cathode surface from which energyin the form of electrons and photons are emitted. The lens array 48 isapplied using conventional thin-film processing and includes a lens 28defined within a conductive layer and aligned with the integratedemitter 100 to focus the energy from the integrated emitter 100 onto asurface of an anode structure 76. Anode structure 76 is located a targetdistance 74 from the integrated circuit 52.

[0027]FIG. 6 is an alternative embodiment of a display application usingthe integrated emitter 100 of the invention. In this embodiment, aplurality of emitters 100 is arraigned and formed in an integratedcircuit 52. Each of the emitters 100 emits energy emission 22 in theform of electron emissions 16 or photon emissions 18 (see FIG. 1). Ananode structure, display 40, receives the emitted energy in displaypixel 44, made up of display sub-pixels 42. Display sub-pixel 42 ispreferably a phosphor material that creates photons when struck by theelectron emission 16 of energy emission 22. Alternatively, displaysub-pixel 42 can be a translucent opening to allow photon emission 18 ofenergy emission 22 to pass through the display 40 for direct photonviewing.

[0028]FIG. 7 is an alternative use of an integrated emitter 100 withinin a storage device. In this exemplary embodiment, an integrated circuit(IC) 52 having a plurality of integrated emitters 100 has a lens array48 of focusing mechanisms aligned with integrated emitters 100. The lensarray 48 is used to create a focused beam 32 that is used to affect arecording surface, media 58. Media 58 is applied to a mover 56 thatpositions the media 58 with respect to the integrated emitters 100 on IC52. Preferably, the mover 56 has a reader circuit 62 integrated within.The reader 62 is shown as an amplifier 68 making a first ohmic contact64 to media 58 and a second ohmic contact 66 to mover 56, preferably asemiconductor or conductor substrate. When a focused beam 32 strikes themedia 58, if the current density of the focused beam is high enough, themedia is phase-changed to create an effected media area 60. When a lowcurrent density focused beam 32 is applied to the media 58 surface,different rates of current flow are detected by amplifier 68 to createreader output 70. Thus, by affecting the media with the energy from theemitter 50, information is stored in the media using structural phasechanged properties of the media. One such phase-change material isIn₂Se₃. Other phase change materials are known to those skilled in theart.

[0029]FIG. 8 is a top view of an exemplary embodiment of the inventionof an integrated emitter 100 that includes an emitter area 84 within thecathode layer 14. The cathode layer 14 is electrically coupled to anddisposed on conductive layer 82 that is disposed over insulator layer78. Integrated emitter 100 is shown as preferably a circular shape,however other shapes can be used. The circular shape is preferable inthat the electric fields generated are more uniform as there are nodiscrete edges within the shape.

[0030]FIG. 9 is a cross-section of the exemplary embodiment ofintegrated emitter 100 shown in FIG. 8 looking into the 9-9 axis. Asubstrate 10, preferably a conductive layer or a highly dopedsemiconductor provides an electron supply to tunneling layer 20 that isdisposed within an opening defined within an insulator layer 78. Acathode layer 14, preferably a thin-film conductive layer is disposedover the tunneling layer 20 and partially over the conductive layer 82thereby making electrical contact with the conductive layer. Optionally,an adhesion layer 80 can added to provide for a bonding interfacebetween the conductive layer 82 and the insulator layer 78 depending onthe particular materials chosen for insulator layer 78 and conductivelayer 82.

[0031]FIG. 10 is an exemplary block diagram of a computer 90 thatincludes a microprocessor 96, memory 98, which is coupled to themicroprocessor 96, and electronic devices, a storage device 94 and adisplay device 92. The electronic devices are coupled to themicroprocessor 96. The microprocessor 96 is capable of executinginstructions from the memory to allow for the transfer of data betweenthe memory and the electronic devices, such as the storage device 94 andthe display device 92. Each electronic device includes an integratedcircuit that has an emitter incorporating the invention and preferably afocusing device for focusing the emissions from the emitter. The emitterhas an electron supply layer with an insulating layer disposed thereon.The insulating layer has an opening defined within which a tunnelinglayer is formed on the electron supply layer. On the tunneling layer isa cathode layer. Preferably but optionally, the integrated circuit withthe emitter has been subjected to an annealing process therebyincreasing the supply of electrons that can tunnel from the electronsupply layer to the cathode layer. The annealing process also reducesthe contact resistance between metal layers thereby enhancingconductivity of electrons to the emitter.

[0032]FIGS. 11A to 11L illustrate exemplary process steps used to createan emitter incorporating the invention. In FIG. 11A, a mask 102, ofdielectrics or photoresist is applied to a substrate 10, preferably asilicon semiconductor substrate, although substrate 10 might be aconductive thin-film layer or a conductive substrate. Preferablysubstrate 10 has a sheet resistance of about 100 to 0.0001 ohmscentimeter.

[0033] In FIG. 11B an insulator layer 78 is created, preferably by fieldoxide growth when substrate 10 is a silicon substrate. Optionally, theinsulator layer 78 can be formed of other oxide, nitride, or otherconventional dielectrics deposited or grown alone or in combinationusing conventional semiconductor processes. The insulator layer 78 iscreated on substrate except in areas covered by mask 102. The areadefined by mask 102, and thus the resulting voids or defined openingswithin insulator layer 78 determines the location and shape of thelatter formed integrated emitter 100 when mask 102 is removed.

[0034] In FIG. 11C, an optional adhesive layer 80 is applied on thesubstrate 10 and insulator layer 78. The adhesive layer 80 is preferablytantalum when the later applied conductive layer 82 (see FIG. 11D) ismade of gold. Preferably, the adhesive layer is applied usingconventional deposition techniques. The adhesive layer is preferablyabout 100 to about 200 Angstroms thick but can be any thicknessdepending on the materials chosen.

[0035] In FIG. 11D a conductive layer 82 is applied on the previouslyapplied layers on substrate 10, such as adhesive layer 80 if used.Preferably, the conductive layer is formed using conventional depositiontechniques. The conductive layer is preferably gold that is about 500 toabout 1000 Angstroms thick.

[0036] In FIG. 11E a patterning layer 104 is applied on the conductivelayer 82 and an opening is formed within it to define an etching regionfor creating the integrated emitter. Preferably, the patterning layer104 is a positive photoresist layer of about 1 um thickness.

[0037] In FIG. 11F preferably a wet etch process is used to create anopening in the conductive layer 82 within the opening of the patterninglayer 104. Typically, the etching will create an isotropic etch profile106 as shown in which a portion of the conductive layer is undercutunder the patterning layer 104. Preferably the wet etch process useddoes not react with the adhesive layer 80, if used, to prevent the etchmaterial from reaching the substrate 10. Optionally, a dry etch processcan be used to etch the conductive layer 82.

[0038] In FIG. 11G preferably a dry etch process that is reactive to theadhesive layer 80 is used to create an anisotropic profile 108.

[0039] In FIG. 11H a tunneling layer 20 of preferably a high dielectricstrength material such as metal cluster dielectrics, TiO_(x), TaO_(x),WSiN, TaAlO_(x)N_(y), TaAlO_(x) or AlO_(x)N_(y), but preferably TiO_(x),is applied over the surface of the processed substrate 10 on thepatterning layer 104 and openings in insulator layer 78. The tunnelinglayer 20 is preferably deposited by sputtering the metal and introducingoxygen and/or nitrogen to form the dielectric to a thickness of lessthan about 500 Angstroms, preferably between about 50 to about 250Angstroms, such as about 100 Angstroms.

[0040] In FIG. 11I a lift-off process is used to remove patterning layer104 and that portion of tunneling layer 20 that is disposed on thepatterning layer 104. Preferably, low temperature plasma is used toreactively etch ash organic materials within the patterning layer 104.The gas used is preferably oxygen in a planer plasma etch process. Theprocessed substrate 10 is place in a chamber and the oxygen isintroduced and excited by an energy source to create a plasma field. Theplasma field energizes the oxygen to a high-energy state, which, in turnoxidizes the patterning layer 104 components to gases that are removedfrom the chamber by a vacuum pump. Because of their proximity anddifference in volume ratios, some of the components of the patterninglayer 104 during lift-off react with constituents in the thin tunnelinglayer 20 disposed on the patterning layer 104. For example, carbonmonoxide released from the patterning layer 104 reacts with the oxygenin a TiO_(x) layer of tunneling layer 20 to form CO₂ gas which is thenremoved leaving a small amount of Ti on the surface of the conductivelayer 82. Thus the tunneling layer 20 disposed on the patterning layer104 is essentially removed in the lift-off process. After the lift-offprocess is complete, essentially only that portion of tunneling layer 20that is disposed within the openings of insulator layer 78 remains.

[0041] Optionally, a wet lift-off process can be used in lieu of theplasma lift-off process. After the tunneling layer 20 is applied to thesurface of the processed substrate 10, the substrate 10 is immersed in asolvent that will swell and remove the patterning layer 104 thus keepingthe tunneling layer 20 disposed within the opening of insulator layer78.

[0042]FIG. 11J shows the application of a cathode layer 14 over thesurface of the processed substrate 10. The cathode layer 14 ispreferably a thin-film metallic layer such as platinum and preferablyhas a thickness of about 50 to about 250 Angstroms. Other metals can beused for cathode layer 14 such as gold, molybdenum, iridium, ruthenium,tantalum, chromium, or other refractive metals or alloys thereof. Thecathode layer 14 disposed on tunneling layer 20 forms the emittersurface 86 within the emitter chamber 114.

[0043]FIG. 11K illustrates the application of a cathode photoresistlayer 116 that has been applied and patterned to define openings wherethe cathode layer 14 is to be etched to isolate multiple emitters on thesubstrate 10.

[0044]FIG. 11L illustrates the cathode layer 14 after it has been etchedand the cathode photoresist 116 removed. Within the emitter chamber 114is the emitter surface 86. An exemplary top view of the resultingstructure is shown in FIG. 8. The emitter surface 86 has a first area.The emitter chamber 114 has a first chamber section interfacing to theemitter surface 86 that has substantially parallel sidewalls within theadhesion layer 80. The emitter chamber 114 has a second chamber sectionformed in the conductive layer 82 that has sidewalls that diverge to anopening having a second area. The second area is larger than the firstarea. The cathode layer 14 is disposed on the emitter surface 86 and thesidewalls of the first and second sections of the emitter chamber 114.By using integrated circuit thin film technology to fabricate theemitter, it can be integrated along with traditional active circuitsfound on conventional integrated circuits. The integrated circuit withthe emitter can be used in display devices or storage devices aspreviously described. Preferably, after fabrication, the emitter issubjected to an annealing process to increase the amount of emissionfrom the emitter.

[0045]FIG. 12A and 12B are charts of exemplary annealing processes whichare used to increase the emission current capability of an emitterembodying the invention. The annealing process also increases the deviceyields and quality by allowing the emitters to last longer. Theannealing process, among other benefits, helps to decrease theresistance of contacts of dissimilar metals thereby increasing thecurrent flow to the emitters.

[0046] In FIG. 12A, a first thermal profile 120 shows the processedsubstrate that includes an emitter incorporating the invention firstelevated to a temperature of about 400 C within 10 minutes then held atthis temperature for 30 minutes. Then the processed substrate is slowlycooled back to room temperature (about 25 C) over a period of about 55minutes.

[0047] In FIG. 12B, a second thermal profile 122 shows the processedsubstrate including an emitter incorporating the invention heated to atemperature of about 600 C within 10 minutes and held at thattemperature for about 30 minutes. Then, the processed substrate isgradually cooled to room temperature over a period of about 100 minutes.Those skilled in the art will appreciate that the elevated temperatureand the rate of cooling can be modified from the exemplary processesdescribed and still meet the spirit and scope of the invention. Byannealing the substrate that includes at least one emitter incorporatingthe invention, several characteristics of the emitter are improved.

What is claimed is: 1-40. (cancelled)
 41. an emitter, comprising: anemitting surface having a first area; a first chamber havingsubstantially parallel sidewalls interfacing to the emitting surface;and a second chamber interfacing to the first chamber and havingsidewalls diverging to an opening having a second area larger than thefirst area.
 42. The emitter of claim 41, further comprising a cathodelayer disposed on the emitting surface, and sidewalls of the first andsecond chambers and wherein the emitter has been subjected to anannealing process thereby increasing the emission capability of theemitter.
 43. The emitter of claim 41 wherein the first chamber is formedwithin an adhesion layer.
 44. The emitter of claim 41 wherein the secondchamber is formed within a conductive layer.
 45. An integrated circuitcomprising at least one emitter of claim
 41. 46. A display devicecomprising at least one emitter of claim
 41. 47. A storage devicecomprising at least one emitter of claim
 41. 48. An integrated circuit,comprising: a conductive surface to provide an electron supply; at leastone emitter formed on the electron supply including, an insulator layerhaving at least one opening to define the location and shape of the atleast one flat emitter device, a conductive layer disposed over theinsulator layer, the conductive layer having at least one opening inalignment with the at least one opening; a tunneling layer disposedwithin the at least one opening of the insulator layer; and a cathodelayer disposed over the tunneling layer and partially over theconductive layer.
 49. The integrated circuit of claim 48 wherein thetunneling layer is a metal cluster dielectric.
 50. The integratedcircuit of claim 48 wherein the tunneling layer has a thickness lessthan about 500 Angstroms.
 51. The integrated circuit of claim 48 whereinthe tunneling layer has a thickness between about 50 Angstroms and about250 Angstroms.
 52. The integrated circuit of claim 48 wherein thetunneling layer is TiO_(x).
 53. The integrated circuit of claim 48wherein the tunneling layer is a metal cluster dielectric selected fromthe group consisting of TaO_(x), WSiN, TaO_(x)N_(y), TaAlO_(x)N_(y),TaAlO_(x), and AlO_(x)N_(y).
 54. The integrated circuit of claim 48wherein the integrated circuit has been subjected to an annealingprocess. 55-71. (Cancelled).